The present disclosure relates to interconnects on substrates and semiconductor packages, and more particularly relates to a semiconductor device including an interconnect extending over different base materials.
In the fields of semiconductor packages, with increasing miniaturization of transistors each formed on a semiconductor chip, the area of the semiconductor chip continues decreasing. Furthermore, with downsizing of devices including a semiconductor package, such as mobile phones, there has been an increasing demand to further downsize semiconductor packages.
To address this demand, wafer level packages (WLPs) or wafer level chip size packages (WL-CSPs) that can be each placed on a printed circuit board with the size of the semiconductor package kept small have been developed. A so-called redistribution layer is formed on each of semiconductor chips at the wafer level, and a solder ball is placed on an electrode connected to the redistribution layer. In this state, the wafer is singulated into semiconductor packages. Such semiconductor packages are referred to as WLPs. The WLPs allow the size of each of the semiconductor packages to be substantially equal to that of each of the semiconductor chips.
However, with increasing functionality required of semiconductor chips, the number of input/output terminals of a semiconductor package increases, and a WLP having a small area cannot include all terminals.
To address this problem, fan out WLPs have been proposed. The fan out WLPs are semiconductor packages that each include an extension surrounding a semiconductor chip and made of a material such as an epoxy resin, a redistribution interconnect extending from immediately above an electrode on the semiconductor chip to immediately above the extension, and solder balls on the semiconductor chip surface including the extension surface. Such semiconductor packages ensure the required number of terminals.
The fan out WLP includes an interconnect straddling the borderline between the principal surface of the semiconductor chip and the principal surface of an epoxy resin body. In addition to the fan out WLP, a semiconductor package that includes a semiconductor chip embedded in a recess formed in a glass epoxy resin substrate also includes an interconnect straddling the borderline between the principal surface of the semiconductor chip and the principal surface of a printed circuit board.
Japanese Unexamined Patent Publication No. 2000-183231 describes a package including an interconnect provided over two different base materials.
FIG. 10 is a perspective view illustrating the configuration of a conventional semiconductor device described in Japanese Unexamined Patent Publication No. 2000-183231. As illustrated in FIG. 10, the conventional semiconductor device includes a semiconductor chip 106 that is flip-chip bonded onto a circuit board 101.
A surface of the circuit board 101 includes circuit sections 103, and a surface of the semiconductor chip 106 includes chip junction portions 107. Interconnects 102 and 104a and junction interconnect portions 104 are formed on the surface of the circuit board 101 so as to be each electrically connected to a corresponding one of the circuit sections 103. The junction interconnect portions 104 are each provided on a corresponding one of low dielectric constant materials 105.
The semiconductor chip 106 is bonded onto the circuit board 101 such that the surface of the circuit board 101 including the circuit sections 103 faces the surface of the semiconductor chip 106 including circuits. In this case, the semiconductor chip 106 is placed on the circuit board 101 such that the chip junction portions 107 each overlap a corresponding one of the junction interconnect portions 104.